Application-specific extensions MIPS architecture

1 application-specific extensions

1.1 mips mcu
1.2 mips16

1.2.1 mips16e
1.2.2 mips16e2


1.3 mips dsp
1.4 mips simd architecture
1.5 mips virtualization
1.6 mips multi-threading
1.7 smartmips
1.8 mdmx
1.9 mips-3d

application-specific extensions

the base mips32 , mips64 architectures can supplemented number of optional architectural extensions, collectively referred application-specific extensions (ases). these ases provide features improve efficiency , performance of workloads, such digital signal processing.

mips mcu

enhancements microcontroller applications. mcu ase (application-specific extension) has been developed extend interrupt controller support, reduce interrupt latency , enhance i/o peripheral control function typically required in microcontroller system designs.

separate priority , vector generation
supports 256 interrupts in eic (external interrupt controller) mode , 8 hardware interrupt pins
provides 16-bit vector offset address
pre-fetching of interrupt exception vector
automated interrupt prologue – adds hardware save , update system status before interrupt handling routine
automated interrupt epilogue – restores system state stored in stack returning interrupt.
interrupt chaining – supports service of pending interrupts without need exit initial interrupt routine, saving cycles required store , restore multiple active interrupts
supports speculative pre-fetching of interrupt vector address. reduces number of interrupt service cycles overlapping memory accesses pipeline flushes , exception prioritization
includes atomic bit set/clear instructions enables bits within i/o register used monitor or control external peripheral functions modified without interruption, ensuring action performed securely.

mips16

mips16 application-specific extension mips through v designed lsi logic , mips technologies, announced on 21 october 1996 alongside first implementation, lsi logic tinyrisc processor. mips16 subsequently licensed nec electronics, philips semiconductors, , toshiba (among others); , implemented extension mips i, ii, iii architectures. mips16 decreases size of application 40% using 16-bit instructions instead of 32-bit instructions , improves power efficiency, instruction cache hit rate, , equivalent in performance base architecture. supported hardware , software development tools mips technologies , other providers.

mips16e

mips16e improved version of mips16 first supported mips32 , mips64 release 1.

mips16e2

mips16e2 improved version of mips16 supported mips32 , mips64 (up release 5). release 6 replaced micromips.

mips dsp

the dsp ase optional extension mips32/mips64 release 2 , newer instruction sets can used accelerate large range of media computations—particularly audio , video. dsp module comprises set of instructions , state in integer pipeline , requires minimal additional logic implement in mips processor cores. revision 2 of ase introduced in second half of 2006. revision adds instructions original ase, otherwise backwards-compatible it.

unlike bulk of mips architecture, s irregular set of operations, many chosen particular relevance key algorithm.

its main novel features (vs original mips32):

saturating arithmetic (when calculation overflows, deliver representable number closest non-overflowed answer).
fixed-point arithmetic on signed 32- , 16-bit fixed-point fractions range of -1 +1 (these called q31 , q15 ).
the existing integer multiplication , multiply-accumulate instructions, deliver results double-size accumulator (called hi/lo , 64 bits on mips32 cpus). dsp ase adds 3 more accumulators, , different flavours of multiply-accumulate.
simd instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed 32-bit register (the 64-bit variant of dsp ase supports larger vectors, too).
simd operations basic arithmetic, shifts , multiply-accumulate type operations.

to make use of mips dsp ase, may:

hand-code in assembly language, time-consuming method of utilizing mips dsp ase, can produce code highest performance.
use asm macros supported gcc produce dsp instructions directly c code.
use intrinsics supported gcc mips dsp ase.
use fixed-point data types , operators in c supported gcc. mips dsp ase processor architecture supports fixed-point data types in general-purpose processor.
use auto-vectorization supported gcc loops via optimization option -ftree-vectorize. advantage of auto-vectorization compiler can recognize scalar variables (which can integer, fixed-point, or floating-point types) in order utilize simd instructions automatically. in ideal case, when auto-vectorization used, there no need use simd variables explicitly.

linux 2.6.12-rc5 starting 2005-05-31 adds support dsp ase. note make use of dsp ase toolchain support required. gcc has support dsp , dspr2.

mips simd architecture

instruction set extensions designed accelerate multimedia.

32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, , 2 x 64 bit vector elements
efficient vector parallel arithmetic operations on integer, fixed-point , floating-point data
operations on absolute value operands
rounding , saturation options available
full precision multiply , multiply-add
conversions between integer, floating-point, , fixed-point data
complete set of vector-level compare , branch instructions no condition flag
vector (1d) , array (2d) shuffle operations
typed load , store instructions endian-independent operation
ieee standard floating-point arithmetic 754-2008 compliant
element precise floating-point exception signaling
pre-defined scalable extensions chips more gates/transistors
accelerates compute-intensive applications in conjunction leveraging generic compiler support
software-programmable solution consumer electronics applications or functions not covered dedicated hardware
emerging data mining, feature extraction, image , video processing, , human-computer interaction applications
high-performance scientific computing

mips virtualization

hardware supported virtualization technology.

mips multi-threading

each multi-threaded mips core can support 2 vpes (virtual processing elements) share single pipeline other hardware resources. however, since each vpe includes complete copy of processor state seen software system, each vpe appears complete standalone processor smp linux operating system. more fine-grained thread processing applications, each vpe capable of supporting 9 tcs allocated across 2 vpes. tcs share common execution unit each has own program counter , core register files each can handle thread software. mips mt architecture allows allocation of processor cycles threads, , sets relative thread priorities optional quality of service (qos) manager block. enables 2 prioritization mechanisms determine flow of information across bus. first mechanism allows user prioritize 1 thread on another. second mechanism used allocate specified ratio of cycles specific threads on time. combined use of both mechanisms allows effective allocation of bandwidth set of threads, , better control of latencies. in real-time systems, system-level determinism critical, , qos block facilitates improvement of predictability of system. hardware designers of advanced systems may replace standard qos block provided mips technologies 1 tuned application.

single-threaded microprocessors today waste many cycles while waiting access memory, considerably limiting system performance. use of multi-threading masks effect of memory latency increasing processor utilization. 1 thread stalls, additional threads instantly fed pipeline , executed, resulting in significant gain in application throughput. users can allocate dedicated processing bandwidth real-time tasks resulting in guaranteed quality of service (qos). mips’ mt technology monitors progress of threads , dynamically takes corrective actions meet or exceed real-time requirements. processor pipeline can achieve 80-90% utilization switching threads during data-dependent stalls or cache misses. of leads improved mobile device user experience, responsiveness increased.

smartmips

smartmips application-specific extension (ase) designed gemplus international , mips technologies improve performance , reduce memory consumption smart card software. supported mips32 only, since smart cards not require capabilities of mips64 processors. few smart cards use smartmips.

mdmx

mips-3d