MIPS32/MIPS64 MIPS architecture

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1 mips32/mips64

1.1 mips32/mips64 release 1
1.2 mips32/mips64 release 2
1.3 mips32/mips64 release 3
1.4 mips32/mips64 release 5
1.5 mips32/mips64 release 6





mips32/mips64

when mips technologies spun-out of silicon graphics in 1998, refocused on embedded market. mips v, each successive version strict superset of previous version, property found problem, , architecture definition changed define 32- , 64-bit architecture: mips32 , mips64. both introduced in 1999. mips32 based on mips ii additional features mips iii, mips iv, , mips v; mips64 based on mips v. nec, toshiba , sibyte (later acquired broadcom) each obtained licenses mips64 announced. philips, lsi logic, idt, raza microelectronics, inc., cavium, loongson technology , ingenic semiconductor have since joined them.


mips32/mips64 release 1

the first release of mips32, based on mips ii, added conditional moves, prefetch instructions, , other features r4000 , r5000 families of 64-bit processors. first release of mips64 adds mips32 mode run 32-bit code. mul , madd (multiply-add) instructions, available in implementations, added mips32 , mips64 specifications, cache control instructions.


mips32/mips64 release 2
mips32/mips64 release 3
mips32/mips64 release 5

announced on december 6, 2012. release 4 skipped because number 4 perceived unlucky in many asian cultures.


mips32/mips64 release 6

mips32/mips64 release 6 in 2014 added following:



a new family of branches no delay slot:

unconditional branches (bc) & branch-and-link (balc) 26-bit offset,
conditional branch on zero/non-zero 21-bit offset,
full set of signed & unsigned conditional branches compare between 2 registers (e.g. bgtuc) or register against 0 (e.g. bgtzc),
full set of branch-and-link compare register against 0 (e.g. bgtzalc).


index jump instructions no delay slot designed support large absolute addresses.
instructions load 16-bit immediates @ bit position 16, 32 or 48, allowing generate large constants.
pc-relative load instructions, address generation large (pc-relative) offsets.
bit-reversal & byte-alignment instructions (previously available dsp extension).
multiply & divide instructions redefined use single register result).
instructions generating truth values generate zeroes or ones instead of clearing/setting 0-bit,
instructions using truth value interpret all-zeroes false instead of looking @ 0-bit.

removed infrequently used instructions:



some conditional moves
branch instructions (deprecated in previous releases).
integer overflow trapping instructions 16-bit immediate
integer accumulator instructions (together hi/lo registers, moved dsp application-specific extension)
unaligned load instructions (lwl & lwr), (requiring ordinary loads & stores support misaligned access, possibly via trapping , addition of new instruction (balign))

reorganized instruction encoding, freeing space future expansions.








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