MIPS I MIPS architecture

1 mips i

1.1 registers
1.2 instruction formats
1.3 cpu instructions

1.3.1 loads , stores
1.3.2 alu
1.3.3 shifts
1.3.4 multiplication , division
1.3.5 jump , branch
1.3.6 exception


1.4 fpu instructions

1.4.1 arithmetic
1.4.2 data transfer
1.4.3 branch

mips i

the first version of mips architecture designed mips computer systems r2000 microprocessor, first mips implementation. both mips , r2000 introduced in 1985. when mips ii introduced, mips renamed mips distinguish new version.

mips load/store architecture (also known register-register architecture); except load/store instructions used access memory, instructions operate on registers.

registers

mips has thirty-two 32-bit general-purpose registers. register $0 hardwired 0 , writes discarded. register $31 link register. integer multiplication , division instructions, run asynchronously other instructions, pair of 32-bit registers, hi , lo, provided. there small set of instructions copying data between general-purpose registers , hi/lo registers.

the program counter has 32 bits. 2 low-order bits contain 0 since mips instructions 32 bits long , aligned natural word boundaries.

instruction formats

instructions divided 3 types: r, , j. every instruction starts 6-bit opcode. in addition opcode, r-type instructions specify 3 registers, shift amount field, , function field; i-type instructions specify 2 registers , 16-bit immediate value; j-type instructions follow opcode 26-bit jump target.

the following 3 formats used core instruction set:

cpu instructions
loads , stores

mips has instructions load , store 8-bit bytes, 16-bit halfwords, , 32-bit words. 1 addressing mode supported: base + displacement. since mips 32-bit architecture, loading quantities fewer 32 bits requires datum either signed- or zero-extended 32 bits. load instructions suffixed unsigned perform 0 extension; otherwise sign extension performed. load instructions source base contents of gpr (rs) , write result gpr (rt). store instructions source base contents of gpr (rs) , store data gpr (rt). load , store instructions compute memory address summing base sign-extended 16-bit immediate. mips requires memory accesses aligned natural word boundaries, otherwise exception signaled. support efficient unaligned memory accesses, there load/store word instructions suffixed left or right . load instructions followed load delay slot. instruction in load delay slot cannot use data loaded load instruction. load delay slot can filled instruction not dependent on load; nop substituted if such instruction cannot found.

alu

mips has instructions perform addition , subtraction. these instructions source operands 2 gprs (rs , rt), , write result third gpr (rd). alternatively, addition can source 1 of operands 16-bit immediate (which sign-extended 32 bits). instructions addition , subtraction have 2 variants: default, exception signaled if result overflows; instructions unsigned suffix not signal exception. overflow check interprets result 32-bit 2 s complement integer.

mips has instructions perform bitwise logical and, or, xor, , nor. these instructions source operands 2 gprs , write result third gpr. and, or, , xor instructions can alternatively source 1 of operands 16-bit immediate (which zero-extended 32 bits).

the set on relation instructions write 1 or 0 destination register if specified relation true or false. these instructions source operands 2 gprs or 1 gpr , 16-bit immediate (which sign-extended 32 bits), , write result third gpr. default, operands interpreted signed integers. variants of these instructions suffixed unsigned interpret operands unsigned integers (even source operand sign-extended 16-bit immediate).

the load immediate upper instruction copies 16-bit immediate high-order 16 bits of gpr. used in conjunction or immediate instruction load 32-bit immediate register.

shifts

mips has instructions perform left , right logical shifts , right arithmetic shifts. operand obtained gpr (rt), , result written gpr (rd). shift distance obtained either gpr (rs) or 5-bit shift amount (the sa field).

multiplication , division

mips has instructions signed , unsigned integer multiplication , division. these instructions source operands 2 gprs , write results pair of 32-bit registers called hi , lo, since may execute separately (and concurrently with) other cpu instructions. multiplication, high- , low-order halves of 64-bit product written hi , lo (respectively). division, quotient written lo , remainder hi. access results, pair of instructions (move hi , move lo) provided copy contents of hi or lo gpr. these instructions interlocked: reads of hi , lo not proceed past unfinished arithmetic instruction write hi , lo. pair of instructions (move hi or move lo) copies contents of gpr hi , lo. these instructions used restore hi , lo original state after exception handling. instructions read hi or lo must separated 2 instructions not write hi or lo.

jump , branch

all mips control flow instructions followed branch delay slot. unless branch delay slot filled instruction performing useful work, nop substituted. mips branch instructions compare contents of gpr (rs) against 0 or gpr (rt) signed integers , branch if specified condition true. control transferred address computed shifting 16-bit offset left 2 bits, sign-extending 18-bit result, , adding 32-bit sign-extended result sum of program counter (instruction address) , 810. jumps have 2 versions: absolute , register-indirect. absolute jumps ( jump , jump , link ) compute address control transferred shifting 26-bit instr_index left 2 bits , concatenating 30-bit result 2 high-order bits of instruction in branch delay slot address s. register-indirect jumps transfer control instruction @ address sourced gpr (rs). address sourced gpr must word-aligned, else exception signaled after instruction in branch delay slot executed. branch , jump instructions link (except jump , link register ) save return address gpr 31. jump , link register instruction permits return address saved writable gpr.

exception

mips has 2 instructions software signal exception: system call , breakpoint. system call used user mode software make kernel calls; , breakpoint used transfer control debugger via kernel s exception handler. both instructions have 20-bit code field can contain operating environment-specific information exception handler.

fpu instructions

mips has 32 floating-point registers. 2 registers paired double precision numbers. odd numbered registers cannot used arithmetic or branching, part of double precision register pair, resulting in 16 usable registers instructions (moves/copies , loads/stores not affected).

arithmetic

data transfer

branch